1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device to realize a reduction of a damage to a gate insulating film resulting from a process of manufacturing a semiconductor, namely, a plasma damage to a gate insulating film.
2. Description of the Related Art
When semiconductor devices are manufactured, various plasma processes are used. The plasma processes include a dry etching, an ashing, a film deposition by means of a plasma CVD method and the like. The plasma implies the existence of an ion having a positive charge and an electron having a negative charge. In this plasma, a balance between the number of the positive charges and the number of the negative charges is usually maintained, and thus, there is no electrical polarization.
However, there may be a case in which the numbers of the positive and the negative charges are not locally uniformed. Thereby an electrical balance is not achieved. In this case, if there is a conductor on a surface of a semiconductor device, the charges in the plasma flow into the semiconductor substrate by way of a gate electrode and a gate insulating film. Thus, a large amount of current flow results in serious problems such as damage or breakdown of the gate insulating film, reliability degradation of LSI, yield loss of LSIs.
Mechanism in which the gate insulating film is damaged will be described below with reference to FIGS. 1 to 6.
FIG. 1 shows a situation after a gate electrode 5 is plasma-etched with a photo resist 8 as a mask. A field insulating film 2 is formed on a P-type semiconductor substrate 1. A gate insulating film 3 is formed on a region surrounded by the field insulating film 2. A gate electrode 5 is formed on the gate insulating film 3, and part of the gate electrode extends on the field insulating film 2.
There is a photo resist 8 having a predetermined shape on the gate electrode 5. A portion of the gate electrode 5 which is not covered with the photo resist 8, namely, a side wall portion 5a is directly exposed to the plasma in the plasma-etching process. As a result, the charges of the plasma flow from the side wall portion 5a into the gate electrode 5. Thus, the gate electrode 5 is electrically charged.
If the amount of the charge is sufficiently large, the charges pass through the gate insulating film 3 and flow into the P-type semiconductor substrate 1. The gate insulating film 3 is damaged when the charges pass through the gate insulating film 3.
FIG. 2 shows a situation after a contact hole is formed in an interlayer insulating film 11. The interlayer insulating film 11 is formed on the entire surface containing the gate electrode 5. A photo resist 12 having a predetermined shape is formed on the interlayer insulating film 11. A hole 5d which penetrates the interlayer insulating film 11 and reaches the gate electrode 5 is formed by the plasma-etching with a photo resist 12 as a mask. A surface portion 5e of the gate electrode 5 is exposed to the plasma, even in this case. Accordingly, the gate insulating film 3 is damaged by the reason similar to the above-mentioned reason.
The following method has been traditionally known as one method of protecting the gate insulating film from being damaged. This is the method of providing an alternate route for the current from the plasma into the semiconductor substrate so that the current from the plasma does not flow into the gate insulating film.
FIGS. 3 to 6 show a method of manufacturing a semiconductor element disclosed in U.S. Pat. No. 5,691,234. This method is a technique referred to as a substrate direct contact or a substrate buried contact.
As shown in FIG. 3, the field insulating films 2 for isolating the elements are formed on the P-type semiconductor substrate 1. The gate insulating film 3 is formed on the regions in which the field insulating films 2 are not formed on the P-type semiconductor substrate 1. Then, as shown in FIG. 4, a part of the gate insulating film 3 is removed. As a result, a substrate contact portion 7 in which the surface of the semiconductor substrate 1 is exposed is formed on the P-type semiconductor substrate 1.
Next, a gate electrode 5 having a predetermined shape is formed on a region containing the field insulating film 2, the gate insulating film 3 and the substrate contact portion 7, as shown in FIG. 5. Moreover, N-type impurity 9a is implanted from the substrate contact portion 7 to the P-type semiconductor substrate 1. As a result, an N-type diffusion layer 10a is formed in the substrate contact portion 7 of the semiconductor substrate 1, as shown in FIG. 6.
As a result, a diode is formed by the N-type diffusion layer 10a and the P-type semiconductor substrate 1. The gate electrode 5 is formed to be in contact with the diode.
This diode functions as described below to protect the device from charging in the plasma process. Polarity of the charging caused by the plasma can be either positive or negative.
If the gate electrode 5 is positively charged, the current does not flow when the charging is small and a voltage is low because the diode does not turn into the breakdown state. When the degree of positive charging is large and the voltage exceeds a certain value, then the diode breakdown occurs. In this case, a large amount of current flow into the P-type semiconductor substrate 1.
On the other hand, if the gate electrode 5 is negatively charged, the diode is biased in a forward direction. As a result, even a low voltage enables the current to flow into the P-type semiconductor substrate 1. Accordingly, the diode of the substrate contact portion 7 can protect the gate electrode 5 from being charged.
However, the above-mentioned conventional method has the problems as described below.
A voltage equal to or higher than a certain value is necessary for the breakdown of the diode, if the voltage applied to the gate electrode 5 is positive. That is, the protection function does not act in a case of the voltage equal to or less than the certain voltage. As an example, let us suppose that a thickness of the gate insulating film is 6 nano-meters. In this case, a breakdown voltage of the gate insulating film 3 is about 8 volts. A breakdown voltage of the diode of the substrate contact portion 7 is about 9 volts. Thus, the gate insulating film 3 is broken before the current flows from the diode into the P-type semiconductor substrate 1.
As the gate insulating film 3 becomes further thinner, the breakdown voltage of the gate insulating film 3 becomes lower. However, the breakdown voltage of the diode can not be substantially changed. Hence, it becomes more difficult to protect the gate insulating film 3 from being damaged.
Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device in which the above-mentioned problems in the conventional method can be overcome, and especially a gate insulating film can be protected regardless of the polarity of the charging of the gate electrode.
The following method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-4092). An insulation layer is formed on a silicon substrate on which a MOS-type field effect transistor is formed. Titanium nitride and tungsten are buried in an open contact hole. Aluminum film, titanium nitride film and silicon oxide film are formed in turn. The silicon oxide film is patterned. Then, the aluminum film is anisotropically etched with the silicon oxide film as a mask. In this case, a part of the aluminum film is left on the insulation layer without perfectly separating various wiring patterns. Next, a side wall is formed on the aluminum film by deposition of the silicon oxide film and etch-back. After this, the aluminum film left on the insulation layer is etched and then the wiring is formed, which solves the above-mentioned charging problems.
The following method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-181220). This method includes the following steps. That is, a gate electrode layer and a semiconductor substrate are short-circuited in a semiconductor device, and a gate electrode is formed through an gate insulating film on the semiconductor substrate. After that, an ion implantation or a plasma process is performed to then cut away a wiring layer through which the gate electrode layer and the semiconductor substrate are short-circuited.
The following method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-232360). An N-channel MOS gate oxide film and a P-channel MOS gate oxide film are formed on a surface of a P-type silicon substrate. N-type impurity is implanted into the P-type silicon substrate through a polysilicon layer on the gate oxide film. Accordingly, a protection diode electrically connected to the polysilicon layer is formed on the P-type silicon substrate. Next, the polysilicon layer is patterned to form a gate electrode. Then, an insulating film is formed on the gate electrode, a contact hole is formed on the insulating film, and an Al wiring electrically connected to the gate electrode is formed inside the contact hole and on the insulating film. Thus, it is possible to suppress the damage concentration on the gate oxide film.
The following method of manufacturing a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-B-Heisei 7-24261). This is a method of manufacturing a semiconductor device having polycide gate structure, and comprises a step of forming a gate insulating film on a semiconductor substrate, a step of a forming a polysilicon layer on this gate insulating film, a step of selectively removing the polysilicon layer and the gate insulating film and forming a hole that reaches a semiconductor substrate, a step of contacting directly with the semiconductor substrate exposed by the hole and the polysilicon layer and then forming a silicide layer and a step of performing ion implantation.
The following method of manufacturing a MOS semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 59-123268). This method comprises a step of providing a wiring layer formed of polysilicon in which part thereof is used as a gate electrode, a step of forming the wiring layer formed of the polysilicon so that when it is connected to an output end of a drive circuit for driving the wiring layer, part thereof is in contact with a semiconductor region serving as the output end of the drive circuit, and a step of forming a metallic wiring layer so as to connect the semiconductor region and the wiring layer formed of the polysilicon to each other after that.